Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál stáhnout pdf (Strana 11)

FIGURES

Slave Controller – IP Core for Xilinx FPGAs III-XI

Figure 61: SyncSignal timing ............................................................................................................... 108

Figure 62: I²C EEPROM signals .......................................................................................................... 109

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál Strana 11