Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál stáhnout pdf (Strana 59)

Example Designs

Slave Controller – IP Core for Xilinx FPGAs III-47

6.1.3 Implementation

1. Open Xilinx ISE

2. Open example design

<IPInst_dir>\example_designs\LX150T_DIGI.xise

3. Generate Programming File

4. Download bitstream to FPGA

6.1.4 SII EEPROM

Use this ESI for the SII EEPROM:

Beckhoff Automation GmbH (Evaluation)/

IP Core example designs ET1815 (Xilinx)/

ET1815 IP Core Avnet LX150T DIGI

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál Strana 59