Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál stáhnout pdf (Strana 44)

IP Core Configuration

III-32 Slave Controller – IP Core for Xilinx FPGAs

5 IP Core Configuration

Figure 12: EtherCAT IP Core Configuration Interface

Parameters pane (top)

The configuration options for the EtherCAT IP Core are available in the IP Core parameters pane at

the top.

Message pane (bottom)

In the lower box additional information like warnings, errors, and EEPROM configuration

recommendations are displayed.

ETHERCAT_XIL_INST (status line)

The status line displays the current ETHERCAT_XIL_INST environment variable, which points to the

EtherCAT IP Core installation directory with the required source files.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál Strana 44