Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál stáhnout pdf (Strana 42)

IP Core Usage

III-30 Slave Controller – IP Core for Xilinx FPGAs

11. The tab "Ports" in the "System Assembly View" shows the connection signals. Connect the

EtherCAT IP Core to other IP and external FPGA pins.

Figure 11: EDK – System Assembly View, Ports tab

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Uživatelský manuál Strana 42