Beckhoff EtherCAT Registers Section II Uživatelský manuál Strana 83

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Distributed Clocks (0x0900:0x09FF)
Slave Controller Register Description II-71
3.49.5 Latch In unit
Table 119: Register Latch0 Control (0x09A8)
ESC20
ET1100
ET1200
IP Core
Bit
Description
ECAT
PDI
Reset Value
0
Latch0 positive edge:
0: Continuous Latch active
1: Single event (only first event active)
r/(w)
r/(w)
0
1
Latch0 negative edge:
0: Continuous Latch active
1: Single event (only first event active)
r/(w)
r/(w)
0
7:2
Reserved, write 0
r/-
r/-
0
NOTE: Write access depends upon setting of 0x0980.4.
Table 120: Register Latch1 Control (0x09A9)
ESC20
ET1100
ET1200
IP Core
Bit
Description
ECAT
PDI
Reset Value
0
Latch1 positive edge:
0: Continuous Latch active
1: Single event (only first event active)
r/(w)
r/(w)
0
1
Latch1 negative edge:
0: Continuous Latch active
1: Single event (only first event active)
r/(w)
r/(w)
0
7:2
Reserved, write 0
r/-
r/-
0
NOTE: Write access depends upon setting of 0x0980.5.
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