
PDI Description
Slave Controller – IP Core for Altera FPGAs III-117
10.5 AXI3 On-Chip Bus
10.5.1 Interface
The AXI3 Slave PDI is selected during the IP Core configuration. The signals of the AXI3 interface
are
:
EtherCAT
IP core
CLK_PDI_EXT
Read address
channel
Read data
channel
Write address
channel
Write data
channel
Write response
channel
IRQ_MAIN
IRQ_DC_SYNC0/1
Figure 57: AXI3 signals
Table 59: AXI3 signals
PDI_AXI_AWID
[PDI_BUS_ID_WIDTH-1:0]
PDI_AXI_WID
[PDI_BUS_ID_WIDTH-1:0]
PDI_AXI_WDATA
[PDI_EXT_BUS_WIDTH-1:0]
PDI_AXI_WSTRB
[PDI_EXT_BUS_WIDTH/8-1:0]
The prefix `PDI_AXI_` or is added to the AXI3 interface signals for the IP Core interface.
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