
Features and Registers
III-22 Slave Controller – IP Core for Altera FPGAs
2.3 Extended ESC Features in User RAM
Table 11: Extended ESC Features (Reset values of User RAM – 0x0F80:0x0FFF)
Number of extended feature bits
IP Core extended features:
0: Not available
1: Available
c: Configurable
Extended DL Control Register (0x0102:0x0103)
AL Status Code Register (0x0134:0x0135)
ECAT Interrupt Mask (0x0200:0x0201)
Configured Station Alias (0x0012:0x0013)
General Purpose Inputs (0x0F18:0x0F1F)
General Purpose Outputs (0x0F10:0x0F17)
AL Event Mask (0x0204:0x0207)
Physical Read/Write Offset (0x0108:0x0109)
Watchdog divider writeable (0x0400:0x04001) and
Watchdog PDI (0x0410:0x0f11)
Watchdog counters (0x0442:0x0443)
Write Protection (0x0020:0x0031)
DC SyncManager Event Times (0x09F0:0x09FF)
ECAT Processing Unit/PDI Error Counter
(0x030C:0x030D)
EEPROM Size configurable (0x0502.7):
0: EEPROM Size fixed to sizes up to 16 Kbit
1: EEPROM Size configurable
Lost Link Counter (0x0310:0x0313)
MII Management Interface (0x0510:0x0515)
Enhanced Link Detection MII
Enhanced Link Detection EBUS
DC Time loop control assigned to PDI
Link detection and configuration by MI
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