
Overview
III-2 Slave Controller – IP Core for Altera FPGAs
1.1 Frame processing order
The frame processing order of the EtherCAT IP Core is as follows (logical port numbers are used):
Table 2: Frame Processing Order
0→EtherCAT Processing Unit→0
0→EtherCAT Processing Unit→1 / 1→0
0→EtherCAT Processing Unit→1 / 1→2 / 2→0 (log. Ports 0,1, and 2)
Figure 2 shows the frame processing in general:
1
Port 1
Auto-
Forwarder
Port 0
Auto-
Forwarder
Loopback function
EtherCAT
Processing Unit
Loopback function
EtherCAT IP Core
port 1 closed
port 1 open
port 0 open
or all ports
closed
port 0 closed
Port 2
Auto-
Forwarder
Loopback function
port 2 closed
port 2 open
Figure 2: Frame Processing
Frame Processing Example with Ports 0 and 1
A frame received at port 0 goes via the Auto-Forwarder and the Loopback function to the EtherCAT
Processing Unit which processes it. Then, the frame is sent to port 1. If port 1 is open, the frame is
sent out at port 1. If it is closed, the frame is forwarded by the Loopback function to port 2. Since port 2
is not configured, the Loopback function of port 2 forwards the frame to the Loopback function of port
0, and then it is sent out at port 0 – back to the master.
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