
Features and Registers
Slave Controller – IP Core for Xilinx FPGAs III-17
Forwarded Rx Error
counter[3:0]
ECAT Processing Unit Error
Counter
Watchdog Time Process Data
Watchdog Status Process Data
Watchdog Counter Process
Data
MII Management Access State
DC – Time Loop Control Unit
DC – Receive Time Latch
mode
DC – Pulse length of
SyncSignals
DC – Latch0 Positive Edge
DC – Latch0 Negative Edge
DC – Latch1 Positive Edge
DC – Latch1 Negative Edge
DC – SyncManager Event
Times
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