Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál stáhnout pdf (Strana 71)

IP Core Signals

Slave Controller – IP Core for Xilinx FPGAs III-59

8 IP Core Signals

The available signals depend on the IP Core configuration.

8.1 General Signals

Table 18: General Signals

Condition

Name

Direction

Description

nRESET

INPUT

Resets all registers of the

IP Core, active low

Reset slave by

ECAT/PDI

RESET_OUT

OUTPUT

Reset by ECAT (reset

high. RESET_OUT has to

trigger nRESET, which

clears RESET_OUT.

CLK25

INPUT

25 MHz clock signal from

PLL (rising edge

synchronous with rising

edge of CLK100)

CLK100

INPUT

100 MHz clock signal from

PLL

1 2 ... 66 67 68 69 70 71 72 73 74 75 76 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál Strana 71