
Features and Registers
III-18 Slave Controller – IP Core for Xilinx FPGAs
General Purpose Outputs
[Byte]
General Purpose Inputs [Byte]
Table 10: Legend
Available if Distributed Clocks with all
Sync/Latch signals are enabled
Available if Receive Times or Distributed Clocks
are enabled (always available for 3-4 ports)
Available if Digital I/O PDI is selected
Register changed in this version
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