Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál stáhnout pdf (Strana 8)

TABLES

III-VIII Slave Controller – IP Core for Xilinx FPGAs

TABLES

Table 1: IP Core Main Features .............................................................................................................. 1

Table 2: Frame Processing Order ........................................................................................................... 2

Table 3: Tested FPGA/Designflow combinations .................................................................................... 5

Table 4: Release notes ............................................................................................................................ 6

Table 5: Register Revision (0x0001) ....................................................................................................... 9

Table 6: Register Build (0x0002:0x0003) ................................................................................................ 9

Table 7: IP Core Feature Details ........................................................................................................... 13

Table 8: Legend ..................................................................................................................................... 15

Table 9: Register availability.................................................................................................................. 16

Table 10: Legend ................................................................................................................................... 18

Table 11: Extended ESC Features (Reset values of User RAM – 0x0F80:0x0FFF) ............................ 19

Table 12: Contents of lib folder.............................................................................................................. 24

Table 13: Resource consumption Avnet LX150T example design ....................................................... 50

Table 14: Resource consumption Avnet LX150T example design ....................................................... 52

Table 15: Resource consumption Xilinx Zynq ZC702 example design ................................................. 54

Table 16: Approximate resource requirements for main configurable functions ................................... 57

Table 17: EtherCAT IP Core resource consumption for typical EtherCAT Devices .............................. 58

Table 18: General Signals ..................................................................................................................... 59

Table 19: SII EEPROM Signals ............................................................................................................. 61

Table 20: LED Signals ........................................................................................................................... 61

Table 21: DC SYNC/LATCH signals ..................................................................................................... 62

Table 22: Physical Layer General ......................................................................................................... 63

Table 23: PHY Interface MII .................................................................................................................. 64

Table 24: PHY Interface RMII................................................................................................................ 66

Table 25: PHY Interface RGMII ............................................................................................................. 67

Table 26: General PDI Signals .............................................................................................................. 70

Table 27: Digital I/O PDI ........................................................................................................................ 70

Table 28: SPI PDI .................................................................................................................................. 71

Table 29: 8/16 Bit µC PDI ...................................................................................................................... 71

Table 30: 8 Bit µC PDI ........................................................................................................................... 72

Table 31: 16 Bit µC PDI ......................................................................................................................... 72

Table 32: PLB PDI ................................................................................................................................. 73

Table 33: PLB PDI additional signals of XPS/EDK pcores ................................................................... 75

Table 34: AXI4 / AXI4 LITE PDI ............................................................................................................ 76

Table 35: AXI4 / AXI4 LITE PDI additional signals of XPS/EDK pcores ............................................... 77

Table 36: PHY management Interface signals ...................................................................................... 78

Table 37: MII management timing characteristics ................................................................................. 79

Table 38: MII Interface signals .............................................................................................................. 81

Table 39: MII TX Timing characteristics ................................................................................................ 83

Table 40: MII timing characteristics ....................................................................................................... 83

Table 41: RMII Interface signals ............................................................................................................ 85

Table 42: RGMII Interface signals ......................................................................................................... 88

Table 43: Available PDIs for EtherCAT IP Core .................................................................................... 91

Table 44: IP core digital I/O signals ....................................................................................................... 92

Table 45: Input/Output byte reference ................................................................................................... 92

Table 46: Digital I/O timing characteristics IP Core ............................................................................... 95

Table 47: SPI signals ............................................................................................................................. 98

Table 48: Address modes ...................................................................................................................... 99

Table 49: SPI commands CMD0 and CMD1 ....................................................................................... 100

Table 50: Interrupt request register transmission ................................................................................ 100

Table 51: Write access for 2 and 4 Byte SPI Masters ......................................................................... 102

Table 52: SPI timing characteristics IP Core ....................................................................................... 103

Table 53: Read/Write timing diagram symbols .................................................................................... 104

Table 54: µController signals ............................................................................................................... 109

Table 55: 8 bit µController interface access types .............................................................................. 110

Table 56: 16 bit µController interface access types ............................................................................ 110

Table 57: µController timing characteristics IP Core ........................................................................... 113

Table 58: PLB signals .......................................................................................................................... 117

Table 59: PLB clock period values for synchronous clocking ............................................................. 118

Table 60: PLB timing characteristics ................................................................................................... 119

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 143 144

Komentáře k této Příručce

Žádné komentáře

Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál Strana 8

Komentáře k této Příručce

Související produkty a manuály pro Zařízení Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k