Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál stáhnout pdf (Strana 9)

TABLES

Slave Controller – IP Core for Xilinx FPGAs III-IX

Table 61: AXI4 LITE signals ................................................................................................................ 121

Table 62: Additional AXI4 signals ........................................................................................................ 122

Table 63: AXI timing characteristics .................................................................................................... 124

Table 64: Distributed Clocks signals ................................................................................................... 126

Table 65: DC SYNC/LATCH timing characteristics IP Core ............................................................... 126

Table 66: I²C EEPROM signals ........................................................................................................... 127

Table 67: EEPROM timing characteristics IP Core ............................................................................. 127

Table 68: AC Characteristics ............................................................................................................... 128

Table 69: Forwarding Delays ............................................................................................................... 128

Table 70: EtherCAT IP Core constraints ............................................................................................. 129

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál Strana 9