Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál stáhnout pdf (Strana 81)

IP Core Signals

Slave Controller – IP Core for Xilinx FPGAs III-69

Condition

Name

Direction

Description

Port2 =

RGMII

nRGMII_LINK2

INPUT

0: 100 Mbit/s (Full

Duplex) link at port 2

1: no link at port 2

RGMII_RX_CLK2

INPUT

Receive clock port 2

RGMII_RX_CTL_DATA_DDR_CLK2

OUTPUT

Receive control/data DDR

input clock port 2

RGMII_RX_CTL_DATA_DDR_NRESET2

OUTPUT

Receive control/data DDR

input reset (port 2, act. low)

RGMII_RX_CTL_DDR_L2

INPUT

Receive control DDR input

low port 2

RGMII_RX_CTL_DDR_H2

INPUT

Receive control DDR input

high port 2

RGMII_RX_DATA_DDR_L2

INPUT

Receive data DDR input

low port 2

RGMII_RX_DATA_DDR_H2

INPUT

Receive data DDR input

high port 2

RGMII_TX_CLK_DDR_CLK2

OUTPUT

Transmit clock DDR output

clock port 2

RGMII_TX_CLK_DDR_NRESET2

OUTPUT

Transmit clock DDR output

reset (port 2, act. low)

RGMII_TX_CLK_DDR_L2

OUTPUT

Transmit clock DDR output

low port 2

RGMII_TX_CLK_DDR_H2

OUTPUT

Transmit clock DDR output

high port 2

RGMII_TX_CTL_DATA_DDR_CLK2

OUTPUT

Transmit control/data DDR

output clock port 2

RGMII_TX_CTL_DATA_DDR_NRESET2

OUTPUT

Transmit control/data DDR

output reset (port 2, act.

low)

RGMII_TX_CTL_DDR_L2

OUTPUT

Transmit control DDR

output low port 2

RGMII_TX_CTL_DDR_H2

OUTPUT

Transmit control DDR

output high port 2

RGMII_TX_DATA_DDR_L2

OUTPUT

Transmit data DDR output

low port 2

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál Strana 81

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