Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál stáhnout pdf (Strana 44)

IP Core Usage

III-32 Slave Controller – IP Core for Xilinx FPGAs

11. The tab "Ports" in the "System Assembly View" shows the connection signals. Connect the

EtherCAT IP Core to other IP and external FPGA pins.

Figure 11: EDK – System Assembly View, Ports tab

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Uživatelský manuál Strana 44